The present invention relates generally to CIS (conductor-insulator-semiconductor) technology and to high-density read-only memories (ROMs).
The rapid implementation of improved process techniques and improved designs has recently provided a multitude of memory subsystems, including the ROM. The ROM may be considered a memory when used in microprogramming applications, or a logic function generator. The ROM subsystem may be thought of as comprising three subsystem functions (1) memory storage provided by an array of memory cells generally defined by the intersection of a matrix of rows and columns of FETs; (2) addressing buffers and decoders for selecting the stored information bits to obtain output signals from the addressed memory; and (3) an output buffer for amplifying the output signals. Conventional ROMs use the presence or absence of a FET to represent binary 1 or 0. That is, the memory cell FET locations are designed, or programmed during processing, to provide an output (FET present) or no output (FET absent) upon the application of an interrogation signal. The conductive/non-conductive, output/nonoutput condition represents bit values 1 and 0 (or vice versa). Conventional ROMs thus can store a maximum of one bit per cell.
To facilitate description of the ROMFETs, we shall not refer to the "presence" or "absence" of a FET, but shall consider every memory cell to contain a FET which either has an output or, for example, has no channel and, thus, no output.
FIG. 1 shows a section of a conventional ROM 10 which uses an m.times.n memory cell matrix. ROM 10 employs one bit per cell memory storage. The illustrated section contains FETs 11, 12, and 21, 22. FETs 12, 21 and 22 become conductive upon the application of a suitable gate voltage. FET 11 has no channel and is incapable of conducting current, at least under normal operating conditions.
Referring further to FIG. 1 and also to FIG. 2, FET 12 comprises a substrate 5 of one conductivity type in which spaced-apart surface-adjacent diffused regions of the opposite conductivity type form a source and a drain. Source 23 is one end of diffusion region 18 (FIG. 1), while drain 24 is a projecting region of diffusion stripe 19 (FIG. 1). (Unless specified otherwise, "diffused" and "diffusion" include doped regions formed by ion implantation techniques as well as by diffusion techniques.)
The gate structure of FET 12 comprises gate dielectric 26 (FIG. 2), typically silicon dioxide, and a polysilicon gate electrode, which is the section of polysilicon row line 15 (FIG. 1) extending between the source 23 and drain 24. Thick, field dielectric layer 27, typically silicon dioxide, electrically isolates the device 12 from other circuit components. Column line 14, which comprises conducting metal such as aluminum, contacts source 23 at 28 for applying control voltages as needed to the source 23 and to other FETs along the column line. Control voltages can be applied at one end of the drain diffusion stripe 19, and at a suitable point along substrate 5. Control voltages can be applied via polysilicon word line 15 to the gate of FET 12 and other FETs in the same row, such as FET 11. When interrogated by a gate signal which is greater than its threshold voltage, FET 12 becomes conductive, representing storage of binary "1".
Referring further to FIG. 1 and also to FIG. 3, FET 11 includes a gate electrode, which is formed by polysilicon word line 15. Metal column line 13 is effectively isolated from word line 15 by oxide layer 31 and crosses over word line 15 to contact diffusion region 17 at 32. However, in contrast to FET 12, FET 11 effectively has no source or drain. That is, the diffusion region 17 is spaced from the gate-forming word line 15 and thus is ineffective as a source. Nor is there a drain-forming region projecting from the diffusion stripe 19. Furthermore, the gate structure is surrounded by oxide layer 31 and is thereby electrically isolated from the channel. Either condition is sufficient to preclude conduction in the FET 11 under normal operating conditions. Thus, when interrogated by a gate signal which is greater than the threshold voltage of the conducting FET 12, FET 11 remains non-conductive, which is indicative of storage of binary "0".
The density of conventional ROM cells such as those of FIG. 1 is limited by the design limitations of current CISFET process techniques. To date, CISFET process technology is capable of providing n channel ROM cell densities of about 400,000 per square centimeter, excluding peripheral circuitry. For ROM cell designs using one bit per cell, comparable bit storage densities are available. With the limitation of ROM designs to one bit per cell, further increases in binary storage capability must come from improved process techniques, e.g., from increasingly precise and expensive techniques such as x-ray or electron beam lithography and ion implanted source and drain regions.
It is thus apparent that it is highly desirable to have ROM designs which provide storage densities greater than one bit per cell, without comparable increases in the physical size of the cell. Such an increase in memory storage density is available in CCD technology, where two bits per cell storage is provided by conventional CCD structures using analog storage techniques. However, to applicant's knowledge, there is no prior art CISFET memory which provide storage densities greater than one bit per cell.